MG82F6D17AL20 Megawin 8051 MCU

The MG82F6D17 is a single-chip microcontroller based on a high performance 1-T architecture 80C51 CPU that executes instructions in 1~7 clock cycles (about 6~7 times the rate of a standard 8051 device), and has an 8051 compatible instruction set. Therefore at the same performance as the standard 8051, the MG82F6D17 can operate at a much lower speed and thereby greatly reduce the power consumption.
The MG82F6D17 has 16K bytes of embedded Flash memory for code and data. The Flash memory can be programmed either in serial writer mode (via ICP, In-Circuit Programming) or in In-System Programming mode. And, it also provides the In-Application Programming (IAP) capability. ICP and ISP allow the user to download new code without removing the microcontroller from the actual end product; IAP means that the device can write non-volatile data in the Flash memory while the application program is running. There needs no external high voltage for programming due to its built-in charge-pumping circuitry.
The MG82F6D17 retains all features of the standard 80C52 with 256 bytes of scratch-pad RAM, two external interrupts, a multi-source 4-level interrupt controller, a serial port (UART0) and three timer/counters. In addition, the MG82F6D17 has17 I/O port pins, one XRAM of 768 bytes, one extra external interrupts with High/low trigger option, 800KHz 12-bit ADC, one 16-bit timer, one 8-channel PCA with dead-time controlled PWM, one 8-bit SPI, two TWI/ I2C (TWI0/ I2C0 and STWI/ SI2C), secondary serial port (UART1), keypad interrupt, Watchdog Timer, Real-Time-Clock module, two Brown-out Detectors, an ECKI external clock input (P6.0), an internal high precision oscillator (IHRCO), an on-chip clock multiplier (CKM) to generate high speed clock source, an internal low speed RC oscillator (ILRCO) and an enhanced serial function in UART0 that facilitates multiprocessor communication, LIN bus mode and a speed improvement mechanism (X2/X4 mode). Support 3 different DMA transfer types, M2P (XRAM to Peripheral), P2M (Peripheral to XRAM) and P2P (Peripheral to Peripheral) to enhance transfer performance and reduce CPU loading.